1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a wiring structure for a pad section in a semiconductor device having bias wirings used as signal paths for a predetermined number of signals.
2. Description of the Prior Art
A pad section in a semiconductor memory device is an area in which a plurality bonding pads including the probe pads for conducting probe tests and wirings that connect, for example, at least the bonding pads to other destinations of the semiconductor memory device are located.
FIG. 1 shows a general layout of a conventional semiconductor memory device including memory array sections 1 and peripheral portions 2.
There are basically three conventional ways to align or arrange a pad section in a semiconductor memory device. A pad section may be aligned in a peripheral portion 2 (the normal type), or in a memory array section 1 (the LOC type), or in both the peripheral portion 2 and the memory array section 1 (the dual pad type).
FIG. 2 is a plan view showing a conventional pad section wiring structure in a semiconductor device, and FIG. 3 is a sectional view taken along the line A–B shown in FIG. 2.
As shown in FIGS. 2 and 3, the conventional pad section of the semiconductor device has the wiring structure that includes: a pad array having a plurality of pads 11 aligned in a row at or near the middle portion of the pad section; a plurality of first bias wirings 13 provided at both sides of the pad array of pads 11 arranged in a row and having different voltage levels; and a plurality of second bias wirings 15 that run perpendicular to the direction of the first bias wirings 13, but in a layer below the layer having the pads 11 and the first bias wirings 13. That is, the pads 11 and the first bias wirings 13 are formed on a common plane above the layer having the second bias wirings. The first and second bias wirings 13, 15 are used as paths for carrying signals to or from the predetermined sources and destinations in the semiconductor device. Referring to FIG. 2, the first bias wirings 13 include Va1, Vb1, Vc1, and Vx1, and the second bias wirings 15 include Vd and Ve.
A bias line 17 runs in parallel with the first bias wirings 11 on one outermost side of the first bias wirings 13 as shown in FIG. 2 and is electrically connected to the second bias wirings 15.
According to the conventional pad section wiring structure described above, each of the first bias wirings 13 (Va1, Vb1, Vc1, and Vx1) aligned at both sides of the pad array-are correspondingly connected to the pads 11 (although the electrical connections between the wirings 13 and the pads 11 are not shown in FIG. 2). This is the reason why the pads 11 and the first bias wirings 13 are generally patterned on a same plane.
In addition, the second bias wirings (Vd and Ve) 15 are patterned on a lower layer of the first bias wirings 13 and are aligned perpendicular to the direction of the first bias wirings 13.
The bias line 17 (Vz1) is formed in the same direction as the first bias wirings 13 on the lowermost layer as shown in FIG. 3.
As semiconductor devices are more highly integrated and equipped with multiple functions, not only the bias wiring structure is becoming more complicated, but also the number of the bias wirings in the semiconductor device is increased. However, the area in a semiconductor device in which to align a pad section to carry those bias wirings is limited.
One obvious method to solve the problem is to enlarge the chip size to accommodate all of the increased number of wirings, but this is not an acceptable solution since the increased chip size will likely cause the produced semiconductor device to be less commercially competitive. Another method to solve the problem is to reduce the width of each wiring and the interval between two adjacent wirings without increasing the chip size, but this will increase the resistance and capacitance of the wirings, thereby lowering the operational performance of the semiconductor device.